1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to resistors formed above the semiconductor layer in complex integrated circuits.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation to provide currently available integrated circuits with an improved degree of performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
Although transistor elements are the dominant circuit element in highly complex integrated circuits which substantially determine the overall performance of these devices, other components, such as capacitors and resistors, may be required, wherein the size of these passive circuit elements may also have to be adjusted with respect to the scaling of the transistor elements in order to not unduly consume valuable chip area. Moreover, the passive circuit elements, such as the resistors, may have to be provided with a high degree of accuracy in order to meet tightly set margins according to the basic circuit design. For example, even in substantially digital circuit designs, corresponding resistance values may have to be provided within tightly set tolerance ranges so as to not unduly contribute to operational instabilities and/or enhanced signal propagation delay. For example, in sophisticated applications, resistors may frequently be provided in the form of “integrated polysilicon” resistors, which may be formed above the semiconductor layer and/or respective isolation structures so as to obtain the desired resistance value without significantly contributing to parasitic capacitance, as may be the case in “buried” resistive structures which may be formed within the active semiconductor layer. A typical polysilicon resistor may thus require the deposition of the basic polysilicon material which may frequently be combined with the deposition of a polysilicon gate electrode material for the transistor elements. During the patterning of the gate electrode structures, the resistors may also be formed, the size of which may significantly depend on the basic specific resistance value of the polysilicon material and the subsequent type of dopant material and concentration that may be incorporated into the resistors so as to adjust the resistance values. Since, typically, the resistance value of doped polysilicon material may be a non-linear function of the dopant concentration, thereby typically requiring specific implantation processes, independent of any other implantation sequences for adjusting the basic transistor characteristic, which may thus result in a moderately high complex manufacturing sequence. Furthermore, due to the ongoing shrinkage of the critical dimensions of the transistors, the resistor elements may also have to be reduced in size, while also typically requiring a reduction of the specific resistance, which in turn may necessitate the usage of higher dopant concentrations. For this reason, in conventional techniques, the demand for reduced specific resistance values of the basic resistor material in view of an overall size reduction of the lateral dimensions of the resistor elements is typically addressed by increasing the dopant dose, which may, however, require an over-proportionally long implantation time, since an increase of the dopant concentration may result in a significantly less pronounced increase of the conductivity due to the non-linear behavior. Furthermore, cycle times for the corresponding implantation processes may also cause increase of the overall process time and may thus contribute to the overall production costs. Therefore, frequently, a different dopant species may be used, which may allow reduced implantation times for a given desired high dopant concentration. In still other approaches, the lateral size of the resistors may be increased so as to obtain the desired resistance values for a given specific resistance, which, however, may not be compatible with the demand for reducing the overall dimensions of integrated circuits in order to provide a reduced chip size, thereby reducing overall production costs, or incorporating an increased amount of functions into a given chip area. In still other conventional approaches, the thickness of the basic polysilicon material may be increased so as to provide an increased cross-sectional area of the corresponding resistor elements, which, however, may require significant modifications of the overall process flow, in particular when polysilicon gate electrodes and the resistors may have to be formed in a common process flow.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.